A Novel NoC Architecture Framework for 3D Chip MPSoC Implementations
نویسنده
چکیده
This paper presents a framework for high-level exploration and RTL design of an optimized Network-on-Chip (NoC) architecture for 3D chips. The RTL is derived from the high-level exploration methodology in a semi-automated way. FPGA implementation figures are given for various implementation parameters of the Network Interface Element, demonstrating the performance/area trade-off of 3D NoC architectures. Additionally, power consumption measurements for 2D and 3D Network Interface Elements are provided for FPGA prototype implementation. Keywords-3D Chips, NoC, FPGA
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